1. Field of the Invention
The present invention relates generally to testing apparatuses and, more particularly, to systems for testing memory devices and methods of using the systems.
2. Description of Related Art
Internal operations of synchronous memory devices, such as synchronous mask read only memory (ROM) devices and synchronous dynamic random access memory (SDRAM) devices, are typically synchronized to a single external clock signal. Such a clock signal synchronization feature can eliminates the need to comply with complex timing requirements of multiple timing strobes typical of asynchronous memory devices. In addition, the memory cells of a typical SDRAM device, for example, are arranged in multiple arrays called banks, instead of as a single array. While one of the banks is being accessed, one or more of the other banks may be readied for subsequent access (e.g., signal lines of the one or more other banks may be precharged). This essentially allows the precharge delay time (latency) to be hidden in memory accesses after a first memory access. In addition, the typical SDRAM device has a “burst mode” capability. In burst mode, an address of a first of a number of desired data values (i.e., a first of a “burst length” of data values) is provided to the SDRAM device. The SDRAM device provides the first data value a number of clock cycles later, then provides the data value at the next address during the next clock cycle, and so on, until the device has provided the burst length of data values.
One known method for testing a memory device involves a “data write” portion followed by a “data read and compare” portion. During the data write portion, a clock signal, address signals, control signals, and data signals are provided to the memory device such that the memory device stores data conveyed by the data signals. The data is preferably test patterns capable of detecting a large number of possible defects in the memory device. The control signals direct the memory device to store (i.e., write) the data signals at the provided (corresponding) addresses. In the case of ROM devices, such as mask ROM devices, a data write operation is not required since the memory cells are pre-programmed.
During the subsequent (or initial, for ROMs) “data read and compare” portion, the clock signal, the address signals, and different control signals are provided to the memory device. This time, the control signals direct the memory device to provide the data stored at the provided addresses. After each data read operation, the data provided by the memory device is compared to expected data, i.e., the data provided to the memory device during the data write portion of the test (or the pre-programmed data in the case of a ROM). If the data provided by the memory device does not match the expected data, a fault is detected in the memory device, and the corresponding address, the data provided by the memory device, and/or the expected data is recorded for future analysis.
Some possible defects of memory devices only become apparent (i.e., result in faults) at or near upper operational frequency limits of the devices. For this reason, most memory device manufacturers test their products “at speed,” meaning at specified maximum signal (e.g., clock signal) frequencies.
For example, where a synchronous memory device has a specified maximum clock signal frequency of 100 MHz, the synchronous memory device is advantageously tested using a 100 MHz clock signal. Where operations of the synchronous memory device are synchronized to a single transition (e.g., a rising edge transition) of the clock signal, a different address is advantageously provided to the synchronous memory device during each cycle of the 100 MHz clock signal.
The above described test method is typically carried out by a testing machine. Testing machines typically store data used to generate at least parts of the clock signal, the address signals, the control signals and/or data signals in data buffer memories (DBMs). A total storage capacity of such DBMs is typically substantially fixed. As the frequency of the clock signal increases, less and less of the DBM storage capacity is typically available for storing data and assisting with the generation of the clock signal, the address signals, the control signals and/or the data signals.
For example, in one known type of tester used to test synchronous memory devices, a size of a portion of the DBM storage capacity available in connection with the generation of test patterns is inversely proportional to the frequency of the clock signal. In such a tester, the maximum DBM storage density may be 144 Mbits (full density) at a selected clock signal frequency (e.g., minimum cycle rate) below 31.25 MHz. Where the clock signal frequency is between 31.25 MHz and 62.5 MHz, the portion of the DBM storage capacity available in connection with the generation of test patterns is 72 Mbits (half density); and where the selected clock signal frequency is between 62.5 MHz and 125 MHz, the portion of the DBM storage capacity available in connection with the generation of test patterns is 36 Mbits (one quarter density). Thus, a memory device having a storage capacity size of 32 Mbits, and having a maximum clock signal frequency of less than 125 MHz, can be tested “at speed” using the known tester (in a single pass). However, a similar 64 Mbit memory device cannot be tested “at speed” in a single pass.
One solution to the above DBM capacity problem has been to test relatively large capacity memory devices in multiple passes, so that different portions of the relatively large capacity devices are tested until the entire storage capacity of the devices has been tested. This incremental testing process is undesirable in that necessary delays between each testing pass can be cumulative, causing the incremental testing process to take a relatively long time.
A need thus exists in the prior art for testing systems which can attenuate the above-described DBM capacity problem, and for new methods of testing memory devices which can reduce or eliminate the DBM capacity problem.